9.2.1. Motherboards, busses, and chipsets

9.2.1.1. * ISA

9.2.1.2. * EISA

9.2.1.3. * VLB

9.2.1.4. PCI

Contributed by Rodney Grimes <rgrimes@FreeBSD.org> .
25 April 1995.

Of the Intel PCI chip sets, the following list describes various types of known-brokenness and the degree of breakage, listed from worst to best.

Mercury:

Cache coherency problems, especially if there are ISA bus masters behind the ISA to PCI bridge chip. Hardware flaw, only known work around is to turn the cache off.

Saturn-I (ie, 82424ZX at rev 0, 1 or 2):

Write back cache coherency problems. Hardware flaw, only known work around is to set the external cache to write-through mode. Upgrade to Saturn-II.

Saturn-II (ie, 82424ZX at rev 3 or 4):

Works fine, but many MB manufactures leave out the external dirty bit SRAM needed for write back operation. Work arounds are either run it in write through mode, or get the dirty bit SRAM installed. (I have these for the ASUS PCI/I-486SP3G rev 1.6 and later boards).

Neptune:

Can not run more than 2 bus master devices. Admitted Intel design flaw. Workarounds include do not run more than 2 bus masters, special hardware design to replace the PCI bus arbiter (appears on Intel Altair board and several other Intel server group MB's). And of course Intel's official answer, move to the Triton chip set, we ``fixed it there''.

Triton:

No known cache coherency or bus master problems, chip set does not implement parity checking. Workaround for parity issue. Wait for Triton-II.

Triton-II:

Unknown, not yet shipping.