All systems based on the IBM-PC and PC/AT have the DMA hardware located at the same I/O ports. The complete list is provided below. Ports assigned to DMA Controller #2 are undefined on non-AT designs.
DMA Address and Count Registers
0x00 write Channel 0 starting address 0x00 read Channel 0 current address 0x02 write Channel 0 starting word count 0x02 read Channel 0 remaining word count 0x04 write Channel 1 starting address 0x04 read Channel 1 current address 0x06 write Channel 1 starting word count 0x06 read Channel 1 remaining word count 0x08 write Channel 2 starting address 0x08 read Channel 2 current address 0x0a write Channel 2 starting word count 0x0a read Channel 2 remaining word count 0x0c write Channel 3 starting address 0x0c read Channel 3 current address 0x0e write Channel 3 starting word count 0x0e read Channel 3 remaining word count
DMA Command Registers
0x10 write Command Register 0x10 read Status Register 0x12 write Request Register 0x12 read - 0x14 write Single Mask Register Bit 0x14 read - 0x16 write Mode Register 0x16 read - 0x18 write Clear LSB/MSB Flip-Flop 0x18 read - 0x1a write Master Clear/Reset 0x1a read Temporary Register 0x1c write Clear Mask Register 0x1c read - 0x1e write Write All Mask Register Bits 0x1e read -
DMA Address and Count Registers
0xc0 write Channel 4 starting address 0xc0 read Channel 4 current address 0xc2 write Channel 4 starting word count 0xc2 read Channel 4 remaining word count 0xc4 write Channel 5 starting address 0xc4 read Channel 5 current address 0xc6 write Channel 5 starting word count 0xc6 read Channel 5 remaining word count 0xc8 write Channel 6 starting address 0xc8 read Channel 6 current address 0xca write Channel 6 starting word count 0xca read Channel 6 remaining word count 0xcc write Channel 7 starting address 0xcc read Channel 7 current address 0xce write Channel 7 starting word count 0xce read Channel 7 remaining word count
DMA Command Registers
0xd0 write Command Register 0xd0 read Status Register 0xd2 write Request Register 0xd2 read - 0xd4 write Single Mask Register Bit 0xd4 read - 0xd6 write Mode Register 0xd6 read - 0xd8 write Clear LSB/MSB Flip-Flop 0xd8 read - 0xda write Master Clear/Reset 0xda read Temporary Register 0xdc write Clear Mask Register 0xdc read - 0xde write Write All Mask Register Bits 0xde read -
0x87 r/w DMA Channel 0 0x83 r/w DMA Channel 1 0x81 r/w DMA Channel 2 0x82 r/w DMA Channel 3 0x8b r/w DMA Channel 5 0x89 r/w DMA Channel 6 0x8a r/w DMA Channel 7 0x8f Refresh